As is known in the art, many electronics applications incorporate both silicon and column III-V circuits due to their unique performance characteristics. The silicon circuits are typically CMOS circuits used for digital signals and the column III-V circuits are for microwave, millimeter wave, and optical signals. Typically this integration is done by fabricating the silicon and column III-V circuits separately on different chips and then electrically connecting them, often with wire bonds. This process is expensive, limits integration complexity, increases the footprint, and introduces parasitic resistances and inductances which degrade circuit performance.
It is also known in the art that transistors have been formed on silicon having <100> and <111> crystallographic orientations (i.e., where, as is well known, a <100> crystallographic orientation is where the <100> axis of the crystalline silicon is normal (i.e., perpendicular) to the layer growing or depositing surface of the silicon and a <111> crystallographic orientation is where the <111> axis of the crystalline silicon is normal (i.e., perpendicular) to the layer growing or depositing surface of the silicon). Many years ago, CMOS was formed on silicon substrates having the <111> crystallographic orientation; however this orientation is inferior for CMOS compared to the <100> crystallographic orientation due to a higher surface state density on the <111> crystallographic orientation.
One CMOS structure is formed on a silicon-on-insulator (SOI) structure. This SOI structure includes a silicon substrate having a <100> crystallographic orientation. An insulating layer of SiO2 is formed on the silicon substrate. An upper device layer of silicon having a <100> crystallographic orientation is formed on the insulating layer, the insulating layer being used to assist electrical isolation of the CMOS transistor devices formed in the upper silicon layer. Thus, both the upper device layer and the substrate have the same crystallographic orientation (i.e., a <100> crystallographic orientation).
It is also known that it is desirable to have silicon CMOS transistors and column III-V (e.g. GaN, GaAs or InP) transistors on a common substrate. One structure used to form CMOS transistors and column III-V transistors on a common substrate is shown in FIG. 1. There, a GaAs transistor is formed on the same substrate as the CMOS transistors. It is also known that GaAs may be grown on a growth layer having a <100> crystallographic orientation It is also known in the art that a column III-V (such as a column III-N, for example, GaN, AlN, GaAlN, InGaN) device can be formed on a silicon substrate. Since it is preferable that the GaN device be formed with <111> crystallographic orientation to minimize crystal defects, the device is typically formed on a substrate (e.g., silicon) having a <111> crystallographic orientation. This device is shown in the middle portion of the structure shown in FIG. 1.
On Jul. 3, 2012, U.S. Pat. No. 8,212,294 was granted, entitled “Structure having silicon CMOS transistors with column III-V transistors on a common substrate”, inventors Hoke et. al., assigned to the same assignee as the present patent application. As described therein, a starting wafer comprises a handle silicon substrate with a <111> orientation, a silicon dioxide insulating layer over a first portion of the <111> substrate, a silicon <100> layer disposed over the insulating layer, and a column III-V device having the same crystallographic orientation as the silicon layer disposed on the second portion of the silicon substrate. More particularly, the semiconductor structure includes a column III-As, column III-P, or column III-Sb device on the <100> silicon layer and is shown in FIG. 1. More particularly, CMOS transistors are formed on one portion of a <100> silicon layer and an MHEMT device, here an InP MHEMT device having column III-As layers, formed on anther portion of the <100> silicon layer. It is noted that the InP MHEMT is in contact with, and is grown along, the <100> crystallographic axis of the silicon layer.
The inventor has recognized that further improvements can be made to the structure described in the above referenced U.S. Pat. No. 8,212,294 (here shown in FIG. 1). More particularly, the inventor has recognized that:
1. The InP MHEMT is not nearly co-planar with the other device surfaces which complicates device processing.
2. The thermal resistance path for heat generated in the InP MHEMT to the substrate is increased by the presence of the silicon layer and SiO2 layer.
3. The growth of III-V material such as the InP MHEMT on a Si <100> surface is improved by tilting the Si<100> surface several degrees. The CMOS process, however, is developed on <100> silicon layers that are not misoriented. Tilting the silicon layer can alter the CMOS process by changing the depths of implanted species.
4. The growth of III-V material such as the MHEMT on a tilted <100> silicon surface is improved by performing a high temperature (˜900 C) anneal to form bilayer steps in the surface. If bilayer steps are not formed, the growth of a binary III-V material on <100> elemental silicon results in antiphase boundary defects. A high temperature anneal could degrade the CMOS and possibly the GaN HEMT present on the wafer.
Having recognized these effects, the inventor discloses herein a non-nitride column III-V or column II-VI device structure, CdTe, HgCdTe or ZnO devices grown on a third portion of a silicon substrate instead of on the silicon <100> layer disposed over the insulating layer.
In one embodiment, a semiconductor structure is provided having: a silicon substrate having a <111> crystallographic orientation; an insulating layer disposed over a first portion of the silicon substrate; a silicon layer having a <100> orientation disposed over the insulating layer, a non-nitride column III-V or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate, the non-nitride column III-V or column II-VI semiconductor layer having formed therein an active device.
In one embodiment, the non-nitride device is a column III-X device, where X is a non-nitride element.
In one embodiment, the column II-VI semiconductor layer is CdTe, HgCdTe or ZnO.
In one embodiment, the column III-X device is a column III-As, column III-P, or column III-Sb device or column III alloys of As, P, and Sb.
In one embodiment, the column III-X device is a InP device
In one embodiment, a III-N layer is in direct contact with a third portion of the substrate, where N is nitrogen.
In one embodiment, the silicon layer has active devices fabricated in it such as CMOS transistor devices formed therein.
With such a structure:
1. The surfaces of the 3 device types, silicon CMOS, GaN HEMT, and InP MHEMT are nearly coplanar.
2. The InP MHEMT is grown directly on the silicon substrate resulting in reduced thermal resistance.
3. The growth of the MHEMT on the substrate eliminates any the need to tilt to the CMOS silicon layer.
4. The steps in a <111> surface are naturally bilayer so the high temperature bilayer anneal is eliminated.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.